package cpu

Import Path
	vendor/golang.org/x/sys/cpu (on golang.org and go.dev)

Dependency Relation
	imports one package, and imported by one package

Involved Source Files
	    byteorder.go
	d-> cpu.go
	    cpu_gc_x86.go
	    cpu_x86.go
	    cpu_x86.s

Exported Type Names


	 type CacheLinePad (struct)
		CacheLinePad is used to pad structs to avoid false sharing.


Exported Values


	  var ARM struct{_ CacheLinePad; HasSWP bool; HasHALF bool; HasTHUMB bool; Has26BIT bool; HasFASTMUL bool; HasFPA bool; HasVFP bool; HasEDSP bool; HasJAVA bool; HasIWMMXT bool; HasCRUNCH bool; HasTHUMBEE bool; HasNEON bool; HasVFPv3 bool; HasVFPv3D16 bool; HasTLS bool; HasVFPv4 bool; HasIDIVA bool; HasIDIVT bool; HasVFPD32 bool; HasLPAE bool; HasEVTSTRM bool; HasAES bool; HasPMULL bool; HasSHA1 bool; HasSHA2 bool; HasCRC32 bool; _ CacheLinePad}
		ARM contains the supported CPU features of the current ARM (32-bit) platform.
		All feature flags are false if:
		  1. the current platform is not arm, or
		  2. the current operating system is not Linux.


	  var ARM64 struct{_ CacheLinePad; HasFP bool; HasASIMD bool; HasEVTSTRM bool; HasAES bool; HasPMULL bool; HasSHA1 bool; HasSHA2 bool; HasCRC32 bool; HasATOMICS bool; HasFPHP bool; HasASIMDHP bool; HasCPUID bool; HasASIMDRDM bool; HasJSCVT bool; HasFCMA bool; HasLRCPC bool; HasDCPOP bool; HasSHA3 bool; HasSM3 bool; HasSM4 bool; HasASIMDDP bool; HasSHA512 bool; HasSVE bool; HasASIMDFHM bool; _ CacheLinePad}
		ARM64 contains the supported CPU features of the
		current ARMv8(aarch64) platform. If the current platform
		is not arm64 then all feature flags are false.


	  var Initialized bool
		Initialized reports whether the CPU features were initialized.

		For some GOOS/GOARCH combinations initialization of the CPU features depends
		on reading an operating specific file, e.g. /proc/self/auxv on linux/arm
		Initialized will report false if reading the file fails.


	  var MIPS64X struct{_ CacheLinePad; HasMSA bool; _ CacheLinePad}
		MIPS64X contains the supported CPU features of the current mips64/mips64le
		platforms. If the current platform is not mips64/mips64le or the current
		operating system is not Linux then all feature flags are false.


	  var PPC64 struct{_ CacheLinePad; HasDARN bool; HasSCV bool; IsPOWER8 bool; IsPOWER9 bool; _ CacheLinePad}
		PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms.
		If the current platform is not ppc64/ppc64le then all feature flags are false.

		For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00,
		since there are no optional categories. There are some exceptions that also
		require kernel support to work (DARN, SCV), so there are feature bits for
		those as well. The minimum processor requirement is POWER8 (ISA 2.07).
		The struct is padded to avoid false sharing.


	  var S390X struct{_ CacheLinePad; HasZARCH bool; HasSTFLE bool; HasLDISP bool; HasEIMM bool; HasDFP bool; HasETF3EH bool; HasMSA bool; HasAES bool; HasAESCBC bool; HasAESCTR bool; HasAESGCM bool; HasGHASH bool; HasSHA1 bool; HasSHA256 bool; HasSHA512 bool; HasSHA3 bool; HasVX bool; HasVXE bool; _ CacheLinePad}
		S390X contains the supported CPU features of the current IBM Z
		(s390x) platform. If the current platform is not IBM Z then all
		feature flags are false.

		S390X is padded to avoid false sharing. Further HasVX is only set
		if the OS supports vector registers in addition to the STFLE
		feature bit being set.


	  var X86 struct{_ CacheLinePad; HasAES bool; HasADX bool; HasAVX bool; HasAVX2 bool; HasBMI1 bool; HasBMI2 bool; HasERMS bool; HasFMA bool; HasOSXSAVE bool; HasPCLMULQDQ bool; HasPOPCNT bool; HasRDRAND bool; HasRDSEED bool; HasSSE2 bool; HasSSE3 bool; HasSSSE3 bool; HasSSE41 bool; HasSSE42 bool; _ CacheLinePad}
		X86 contains the supported CPU features of the
		current X86/AMD64 platform. If the current platform
		is not X86/AMD64 then all feature flags are false.

		X86 is padded to avoid false sharing. Further the HasAVX
		and HasAVX2 are only set if the OS supports XMM and YMM
		registers in addition to the CPUID feature bit being set.